Broadcom's follow-on act to the trident+ switch integrated circuit is the shiny new StrataXGS Trident II BCM56850.

  • BCM56850 Used for switches with 32 x 40 Gb/s ports
  • BCM56854 Used for switches w 48 z 10 Gb/s and 6 x 40 Gb/s ports

    It was announced in 2012, but became available in production volumes in November 2013. Broadcom does not share detailed information about their products except under nondisclosure. But you can guess that -- if a new switch was introduced in November or December of 2013 and it has lots of 40 Gb/s ports, well -- it walks like a duck.

    We believe that Broadcom has wins from switch manufacturers Arista, Cisco and Extreme Networks -- that have been spotted so far.

    In common with the trident+, all the packet buffers are on the switch chip. Where the Trident+ has 9 MBytes of packet buffers, the Trident II has 12 Mbytes. The memory is segmented into dedicated per-port buffers and a dynamic shared pool that can be loaned to any queue and port that needs it. Most of the memory is in the shared pool. For more information, see the listing for the Arista 7050X. While we have not seen switches implemented with more than a single Trident+ chip, the Trident II can be used in larger switches with crossbar connections between switching elements. The Arista 7250 is an example.

    One of the new features introduced with the Trident2 is support for VXLAN. Specifically, the Trident2 has support for NVGRE (Network Virtualization General Route Encapsulation). This will stimulate a raft of switches with data center features built on Trident II silicon. For more information see the blogs at

    The 56850 has 128 SERDES to provision 32 quad ports. If this was used for 1RU switches with 10 Gb/s ports, 48 SERDES would be stranded in the box with no place to connect. That seems like it would be sufficient reason to have the 56854 varient.

    Update April 2015 -- Trident-II+ BCM56860 announced

    The trident was followed by the trident+. Thus it is with the trident-II. Details in the press release. The new chip is made with 28 nM features which is a step smaller than the 40 nM geometries in its predecessor. VxLAN performance is also much better. The II+ can support eight 100 Gb/s ports. It is built with 10 Gb/s SERDES and so requires an external gearbox IC to step up to 25 Gb/s lanes. P/N for gearbox BCM82792.

    StrataXGS Trident-II+ (BCM56860) Series Key Features

  • Standards-compliant high-density 10GbE/40GbE/100GbE switch SoC
  • Single-pass routing in/out of tunnels (RIOT) at 1.28 Tbps
  • High-performance tunneling support for VXLAN, NVGRE, MPLS, SPB, and pre-standard Geneve
  • 128 low-power optimized 10Gbps serial interfaces with up to 8 ports of 100GbE
  • Broadview™ instrumentation featuring buffer statistics tracking (BST) and flex counters
  • Enhanced ContentAware engines with 4x larger ACL rule databases versus previous generation devices
  • OpenFlow 1.3.1+ support scaling to several 10,000's of flows using OF-DPA and third-party controllers
  • Configurable SmartTable technology to maximize L2 MAC,L3 Host, LPM forwarding database capacities
  • Full IPv4 and IPv6 unicast and multicast routing support
  • Integrated SmartBuffer for optimal burst absorption, dynamic thresholding and lossless service
  • SmartHash™ flexible engine featuring highly scalable ECMP load balancing and network resiliency
  • FlexPort technology enables dynamically configurable ports/MACs
  • Ethernet Port Multiplier technology supports fine-grained channelization over Ethernet and enterprise fabrics

    Trident 2 vs Mellanox SX

    Mellanox commissioned (paid) Tolly to do comparison tests against an Arista switch representing the universe of Trident-II products. Tolly was able to show that the Mellanox SX was better than the Broadcom Trident-II when the packet rate is really high. That happens when there are lots of small frames. The Tolly report is #215111.

    Especially interesting is the claim that Trident drops out of cut-thru mode to store and forward whenever more than one speed is present in the port ensemble. Mellanox doesn't do this, so can show lower port-to-port latency. Tolly presents this suprising result in figure 2:

    Pure speculation: Because Mellanox dedicates memory to each output port, each buffer chunk will be fed out at a known speed and cut-through rules can be followed. Because Trident shares memory, any buffer chunck might be headed for any port, so changing the mode of the switch when speed matching happens anywhere might be the best solution. The RFC2544 test seems carefully constructed to assure that buffers aren't stressed.