Innovium Teralynx

Public announcement date: March 14, 2017

A family of chips aimed at the data center with hopes of eating Broadcom's lunch. New high watermark with 70 MB buffer on-chip packet memory. This is just an announcement -- no product yet.

SKU/Part      Capacity 	Number of 	100G Ports	200G Ports	400G Ports
 Number	       (Tbps)   SerDes @ Gbps  
IVM77700	12.8	256 @ 10/25/50	  128		   64		   32
IVM77600	9.6	192 @ 10/25/50	   96		   48		   24
IVM77500	6.4	256 @ 10/25	   64		   32		   .
IVM77520	6.4	128 @ 10/25/50	   64		   32		   16
IVM77300	3.2	128 @ 10/25	   32		   16		   .

There is a white paper. And there is a a PR-based trade magazine article.

To get 128 QSFP28 ports requires either 512 SERDES or 256 SERDES and an appropriate gearbox to split a single 50 G PAM4 lane into two 25 G NRZ lanes. These devices are made by Inphi.

March 22, 2018 update

Innovium presented a slide at the 2018 OpenCompute Summit announcing that the milestone of sampling had been reached.

At this point, samples will be sent to qualified manufacturers who will prototype and build products. So, nothing that can be ordered. I asked whether the buffer was a single unified pool. Answer: you need to sign a non-disclosure to find out. What that means is -- no -- it is not unified. It is segmented in a proprietary manner.

Teralynx was the top dog switch at 12.8 Tb/s in the category of vaporware. That ended with Broadcom's Tomahawk 3 announcement at the end of 2017 because Broadcom was shipping samples to their whitebox vendors. With Teralynx's March announcement, they are now shipping as well.


This page had a table showing switch performance evolution. It was poorly placed and has been moved.