Innovium Teralynx 7
Public announcement date: March 14, 2017
A family of chips aimed at the data center with hopes of eating Broadcom's lunch. New high watermark with 70 MB buffer on-chip packet memory. This is just an announcement -- no product yet.
To get 128 QSFP28 ports requires either 512 SERDES or 256 SERDES and an appropriate gearbox to split a single 50 G PAM4 lane into two 25 G NRZ lanes. These devices are made by Inphi.
March 22, 2018 update
Innovium presented a slide at the 2018 OpenCompute Summit announcing that the milestone of sampling had been reached.
At this point, samples will be sent to qualified manufacturers who will prototype and build products. So, nothing that can be ordered. I asked on the OpenCompute show floor whether the buffer was a single unified pool. Answer: you need to sign a non-disclosure to find out. Innovium claims that the Teralynx latency is the best in the industry. Tomahawk 3 is specified by several of their OEMs [e.g. Arista] as 700 nS. Cisco clocks their 3432D Teralyx as 370 nS. With that performance, it is unlikely that the Teralynx has a slice architecture.
There are momma bear, papa bear, baby bear versions of the Teralynx 7 ASIC:
Teralynx was the top dog switch at 12.8 Tb/s in the category of vaporware. That ended with Broadcom's Tomahawk 3 announcement at the end of 2017 because Broadcom was shipping samples to their whitebox vendors. With Teralynx's March announcement, they are now shipping as well.
May 2020 update
TERALYNX 8 Family Highlights
April 2021 update
Article in The Next Platform announces that innovium has done a SONiC port for Teralynx. It appears that design wins for Teralynx have been mostly private. Perhaps that will change. Innovium is rumored to be used in AWS and confirmed at LinkedIn. There may be ODM products aimed at second tier users, given the SONiC port. Anyway, read the article.
This page had a table showing switch performance evolution. It was poorly placed and has been moved.