Innovium Teralynx 7

Public announcement date: March 14, 2017

A family of chips aimed at the data center with hopes of eating Broadcom's lunch. New high watermark with 70 MB buffer on-chip packet memory. This is just an announcement -- no product yet.

There is a white paper. And there is a a PR-based trade magazine article.

To get 128 QSFP28 ports requires either 512 SERDES or 256 SERDES and an appropriate gearbox to split a single 50 G PAM4 lane into two 25 G NRZ lanes. These devices are made by Inphi.

March 22, 2018 update

Innovium presented a slide at the 2018 OpenCompute Summit announcing that the milestone of sampling had been reached.

At this point, samples will be sent to qualified manufacturers who will prototype and build products. So, nothing that can be ordered. I asked on the OpenCompute show floor whether the buffer was a single unified pool. Answer: you need to sign a non-disclosure to find out. Innovium claims that the Teralynx latency is the best in the industry. Tomahawk 3 is specified by several of their OEMs [e.g. Arista] as 700 nS. Cisco clocks their 3432D Teralyx as 370 nS. With that performance, it is unlikely that the Teralynx has a slice architecture.

There are momma bear, papa bear, baby bear versions of the Teralynx 7 ASIC:

Part Numbers	Capacity (Tbps)	Number of SerDes @ Gbps	10/25/50G Ports	100G Ports	200G Ports	400G Ports
Teralynx 8
IVM88700	25.6	256@ 10/25/50/100	256	256	128	64
IVM88500	12.8	256 @ 10/25/50	128	128	64	32
IVM88300	8.0	160 @ 10/25/50	80	80	40	20
Teralynx 7
IVM77700	12.8	256 @ 10/25/50	168	128	64	32
IVM77600	8.0	160 @ 10/25/50	160	80	40	20
IVM77500	6.4	256 @ 10/25	168	64	32	–
IVM77510	6.4	128 @ 10/25/50	128	64	32	16
IVM77310	3.2	128 @ 10/25	128	32	16	–
Teralynx 5
IVM55610	6.4	128 @ 10/25/50	128	64	32	16
IVM55510	4.8	128 @ 10/25/50	128	64	32	16
IVM55300	3.2	128 @ 10/25	128	32	16	-
IVM55200	2.4	96 @ 10/25	96	24	12	-
IVM55100	1.2	48 @ 10/25	48	12	6	-

Teralynx was the top dog switch at 12.8 Tb/s in the category of vaporware. That ended with Broadcom's Tomahawk 3 announcement at the end of 2017 because Broadcom was shipping samples to their whitebox vendors. With Teralynx's March announcement, they are now shipping as well.

May 2020 update

TERALYNX 8 Family Highlights

• Robust 112G SerDes IO with best economics for next-generation switches
  • Up to 256 long-reach (LR) 112G PAM4 SerDes to enable switch configurations such as 32 x 800G, 64 x 400G, 128 x 200 and 256 x 100G
  • Enables industry’s most compact 32 x 800G (25.6 Tbps) switch in 1RU form factor
  • Enables a range of connectivity options, including 10/25/50/100/200/400 GbE
• TERASCALE fabric delivers industry’s most scalable interconnect with lowest latency
  • Range of pin-compatible SKU options, including 25.6 Tbps, 12.8 Tbps and 8Tbps
  • Largest on-chip buffer of 170 MB for a data-center switch
  • Highest radix with 256 ports to help flatten network tiers

April 2021 update

Article in The Next Platform announces that innovium has done a SONiC port for Teralynx. It appears that design wins for Teralynx have been mostly private. Perhaps that will change. Innovium is rumored to be used in AWS and confirmed at LinkedIn. There may be ODM products aimed at second tier users, given the SONiC port. Anyway, read the article.