Table is intended to show performance enhancement of switch ASICs -- arranged chronologically by announcement date. Cisco announces their new silicon along with its first products while merchant silicon manufacturers announce new ASICs perhaps a year before their customers are ready to ship first products. Where buffer is shown with a multiplier, the ASIC design is segmented. Total packet buffer is the product of the numbers in the buffer column but only the segment amount is available to any one output port.

ASICAnnounced buffer Geometry Sw BW
Cisco Cat3550Dec 2001 2 Mbyte 8.8 Gb/s
HP Procurve ASICMar 20030.5 Mbyte 48 Gb/s
Broadcom BCM56314Mar 20070.75 Mbyte 48 Gb/s
Broadcom Trident+Mar 20109 Mbyte 40 nM 0.64 Tb/s
Broadcom Trident IIAug 201212 Mbyte 40 nM 1.28 Tb/s
Cisco AlgoboostSep 201218 Mbyte 480 Gb/s
Cisco UADP 1.0Jan 20136 Mbyte 36 nM 56 Gb/s
Cavium XpliantSep 201424 Mbyte 28 nM3.2 Tbps
Broadcom TomahawkSep 20144 x 4 Mbyte 28 nM3.2 Tbps
Broadcom Trident II+Apr 201516 Mbyte 28 nM 1.28 Tb/s
Mellanox SpectrumJune 201516 Mbyte 28 nM 6.4 Tbps
Broadcom Tomahawk-IIOct 20164 x 10.5 Mbyte 16 nM6.4 Tbps
Innovium TeralynxMar 201770 Mbyte 16 nM12.8 Tbps
Broadcom Trident IIIJune 201732 Mbyte 16 nM3.2 Tbps
Cisco UADP 2.0June 20172 x 16 Mbyte 28 nM240 Gb/s
Broadcom Tomahawk-3Dec 201764 Mbyte 16 nM12.8 Tbps
Cisco UADP 3.0Mar 201836 Mbyte 16 nM1.6 Tbps