C9300-24T introduced July 2017

C9300-48T introduced July 2017

C9300-24UX introduced Nov 2017

These switches are the successor to the Catalyst 3850. C3850s use the UADP 1.0 and (later) 1.1 ASICs. The C9300s use the UADP 2.0 custom Cisco silicon. The entire family is stackable switches. The bus that interconnects stack members runs at 480 Gb/s. But individual stack members probably contain multiple ASICs or multi-core ASICs that also use the stack system internally for core-to-core interconnect. The stacking architecture permits packets to be recirculated through the switch processing engine to implement things like VxLAN routing. In product videos cisco hypes recirulation as a major enhancement that teaches old ASICs new tricks. Other vendors have pipeline architectures with multiple stages to achieve the same end. That may be a better idea. Words about the UADP 1.0 are relevant to these products as well.

What Cisco has to say about packet buffers is:

Packet Buffer per SKU16 MB buffer for 24- or 48-port Gigabit Ethernet models
32 MB buffer for 24-port Multigig models

This was extracted from table 4 of the 24-page data sheet. The information is less than satisfying. Perhaps Cisco will publish a real architecture paper. If the multigig UX model uses the same UADP ASIC as the gig-E models, then the per-core buffer would be the same. So, it's a mystery. It does seem that the UADP 2.0 core engine has more packet memory than the 6 MB of the 1.1 predecessor. Buffer per SKU is not what we want to know. We want buffer per core.

Uplink modules

The C9300 switches can use uplink modules from its C3850 predecessor. In addition, it has it's own models which are not backward compatible to the C3850.

Catalyst C9500

C9500-24Q introduced July 2017

C9500-40X introduced September 2017

These C9500s use the same UADP 2.0 ASIC as the C9300s. Other SKUs in the C9500 family -- distinguished by SERDES running at 25 Gb/s -- use the UADP 3.0.

Last update 7 Nov 2018.