Introduced in January 2013, the Catalyst 3850 is a step along the path of 1 RU access switches and the successor to the 3750X.

It is powered by the new UADP ASIC. UADP stands for Unified Access Data Plane. What is unified is that in addition to a shared memory switch function, the silicon runs the CAPWAP protocol in hardware to give really fast WiFi performance. Three of the UADP ASICs are used in the 5760 Wireless Lan Controller to provide 60 Gb/s of WiFi capacity. In the 3850 switches, an ASIC is used to host 24 ports. A 48 port switch has two UADP ASICs. The same ASIC runs the 3650, a version without the stacking capability.

It is remarkably difficult to get hard info on buffer allocations for this switch, although it appears to be available to those with a big checkbook:

End-to-End QoS Network Design: Quality of Service for Rich-Media & Cloud Networks, 2nd Edition
By Tim Szigeti, Christina Hattingh, Robert Barton, Kenneth Briley Published Nov 26, 2013 by Cisco Press. Part of the Networking Technology series.

In unrestricted public information Cisco has the following table that shows, from 20,000 ft, the progression of ASICs.

Above, Buffers/48 port means buffers in the 48 port switch. Twenty-four port models have half the packet buffers. A per-ASIC view of the 3850 ASIC buffer resources shows this:

While this slide is in the deck for BRKARC-3438, in the recorded video this image did not appear. Discussing queue allocation may be the kind of thing that can turn a 90 minute talk into a two hour marathon. Based on discussions of queue borrowing in the catalyst 3560E, it is likely that UADP can be configured to treat a portion of the egress queue as a pool that can be dynamicly allocated. To verify this, I would need to buy the book.

Catalyst C3850-12XS and C3850-24XS

The 12- and 24-port SFP+ variants of the Catalyst 3850 were introduced in June 2015 at the San Diego Networkers. The slide deck from the Networkers breakout session makes it explicit how many ports are hosted on an ASIC or core. Terminology is slightly strained; ASICs with dual cores behave like two independent ASICs. One core can serve six 10 Gb/s ports on the front panel and two 10 Gb/s ports on the uplink module. The packet memory pie chart for the other 3850 models [above] applies to the XS models, too.

There will be a 48 port version of the XS switch, but it will not be orderable for a while.

table shows ports per switch ASIC

Catalyst 3850 switches can accept uplink modules with both SFP and SFP+ ports:

uplink module photos