Walter Arevalo

Computer Engineering Student - UC Santa Cruz

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UC Santa Cruz student interested in Processor Design and Logic Systems. Currently working on Embedded Systems.

Job Experiences

Jun. 2022 - Present

Lead Technician, ResNet - Santa Cruz, CA

Help clients with technical questions including Network Configuration, Network Registration, and Diagnosing and Fixing Software Issues. Designed marketing materials, websites, and campus-wide publications. Hired, trained, and supervised a team of 20 support technicians.
Aug. 2021 - Jun. 2022

Technician, ResNet- Santa Cruz, CA

Diagnosed endpoint issues with enterprise network serving over 9,000 residents. Provided hands-on and remote support with desktop and mobile devices.

Education

Sept. 2018 - May 2023

University of California, Santa Cruz

B.S Computer Engineering
Sept. 2014 - May 2018

Granda Hills Charter High School

Leadership

Sept. 2019 - Present

Porter College Senate Chair

Lead the University's residential college student government. Ran events as well as used student funds to better the student experience for a college of over 1,700 students. Provided funding for clubs, student interests, and college renovation projects.




Sept. 2014 - May 2018

Granda Hills Charter High School

CSE

125

Logic Design with Verilog

Used behavioral and structural verilog to create various designs. Used Verilog verification software to understand the verification of FPGA. Optimized designs in regard to LUTs and FFs.
CSE

121

Embedded System Design

Created an Embedded system using PSoC and Arduino. Created Drivers for PSoCs and learned to use I2C and various protocols as well as coding in x86.

  1. Computer Skills

    Python, C/C++

  2. Verilog (Behavioral and Structural)

  3. Relevant Software

    Xilinx Vivado

  4. PSoC Creator