Cisco 8000 Silicon One

Fancy public announcement in 12 December 2019

This slide taken without permission from Lane Wigley's presentation at Networkers Barcelona.

In a webcast event on December 12, 2019 that lasted over one hour, Cisco managed to sing high praises without disclosing any content of technical interest. The project was 5 years in the making and cost $1B to develop. Silicon One will be a family of ASICs, the first of which is the Q100. At Cisco Live! in Barcelona at the end of January 2020 Lane Wigley talked in breakout session BRKSPG-2280 to describe the new product line and describe technical content. Some form of registration or club membership may be required to access the recording.

Broadcom has ASIC families -- each tuned to its task in the network hierarchy. Tomahawk is the least flexible where all effort has been given over to blinding speed; Trident has more flexibility and programmability; Jericho has deep buffers but less speed. Broadcom's crossbar element for the Jericho family is Ramon, so yet another ASIC. Cisco's Silicon One will do it all in a single architecture. The Silicon One Q100 has 16 nm feature size.

Jericho2 and Cisco's Q100 have in common that they both use HBM memory connected to the switching ASIC at the chiplet level. This either improves speed or saves power. Those are probably the same thing. All Broadcom switch ASICs dice packets into cells. The cells, typically about 256 Bytes, are moved to the output port where they are reassembled into packets. This works well for cut-through switching. Silicon One moves packets through the switch as packets. This has the advantage that there is no difference between internal ports that connect to the interchip fabric elements and the panel ports at the edge of the device that connect to the outside world.

Cut-through switching is of little use to routers. And the first use of Silicon One is to build routers. We are promised that the Silicon One architecture is good for everything and that it will pop up all over Cisco's products, perhaps with the Q100 ASIC or perhaps with some other as yet unannounced ASIC.

In January 2020 Lawrence Wobker presenting at Tech Field Day disclosed the packet memory of the Q100 ASIC is 8 GB of HBM.

At this writing [June 2020] there is no ordering guide and no pricing which means that the products have not reached general availability. But soon.

Update

The 8201 and 8202 are on the February 2021 price list, so orderable. New family members introduced in October 2020 using silicon with 7 nm features. Q200 parts have HBM chiplet off-die memory and are intended for routing. Q200L parts do not have off-die memory and are intended for switching. Cisco has not disclosed packet memory for Silicon One. They have said that it is big. The following graphic shows ten family members. It first appeared in a Cisco blog:

The G100 part was introduced March 11, 2021. Its distinguishing feature is PAM4 SerDes that run at 112 Gb/s yielding 100 Gb/s lanes and 800 Gb/s QFP-DD interface speeds. There is a white paper that describes the parts that have been introduced as of March 2021.

Update 2

Update 3

Description of the internal packet buffer remains Large, fully shared, on-die packet buffer without dislosure of the packet buffer size. Cisco does have an extensive paper on Silicon One's buffer architecture. http://people.ucsc.edu/~warner/Bufs/silicon-one-buffer.pdf. All the examples of different types of buffer architecture not withstanding, it does not give us the answer to the how much buffer question. It supports a guess that the 7 nM parts have 100 Mbyte of packet buffer.