Announced 14 June 2017
We have a press release.
There is a information sheet [june 2017]
Broadcom says that the Trident3 has a unified buffer, unlike the segmented buffer of the Tomahawk. X7, X5 and X4 have 32 Mbyte packet buffer. X3 has 8 Mbyte of packet buffer. The silicon geometry is 16 nm, same as the Trident2+. Best info so far is a PacketPushers blog posting. But you should read the post on their blog site to enjoy the fine discussion that follows.
Sometime after the information sheet, it became clear that there are two versions of the X4 varient:
Arista has an architecture paper [March 29, 2018] with useful detail about Trident-3 that has not been released by Broadcom. Compare with figure 5 in the Trident2 architecture paper. Internals block diagram of the Trident-3:
A point made by Tofino and the P4 proponents is that having identical pipeline stages makes it easier to reuse the chip for new protocols.
The Trident3 has been designed with Broadview fine grained performance monitoring in mind, so there's an information sheet on that. A sample look at a microburst as seen by the Trident3:
independent software tooled up for the Trident-3.
Tristan Suerink has tested Trident3 and found that its throughput claims are exagerated. Slides from his March 2019 talk: https://indico.cern.ch/event/765497/contributions/3348837/attachments/1818608/2973449/Hepix-2019-San-Diego.pdf