Announced Christmas 2017.
There are lots of trade rag articles that all seem to have been derived from Broadcom's product press release. I will not regurgitate.
For those attempting to keep the team roster in order, a similar announcement for this ASIC's predecessor used Roman numerals (tomahawk-ii) while the new part is Tomahawk 3. It is probably not right to make a big deal about this. Broadcom has dedicated two part numbers:
There are 256 Serdes in the parent BCM56980 part. Each runs at 50 Gb/s, so 12.8 Tb/s. Through the power of long division, the BCM56982 part will have 160 Serdes. Off into the world of wild speculation, a single 400 Gb/s port will have eight lanes. So there's a new QSFP-DD format with twice the lane density. A Top of Rack configuration might have 48 100 Gb/s ports along with eight 400 Gb/s uplink ports. It would need 160 Serdes. Something like that. To break the ports out at 100 Gb/s will result in 128 ports with 2 lanes each. That works for 2 x 50 Gb/s lanes, but that has no backward capability with QSFP28 which uses 4 lanes. Inphi makes gearbox ASICs that can break a 50 Gb/s PAM4 lane in to two NRZ 25 Gb/s lanes.
There is a series announcement.
Since there are no products for this just-announced ASIC, it is interesting to consider the design challenges at this density. The IEEE has been doing just that.
Update March 2018
Broadcom disclosed some additional details in a press release slide deck. To perhaps unfairly emphasize a single feature, Tomahawk-3 has fixed the muliple slice architecture with a unified buffer controlled by a fancy new MMU. On the not-so-good side, BCM remains shy about disclosing the amount of packet memory. Tomahawk and Tomahawk-ii have their packet memory divided into four separate chunks, each managed by its own slice.
In October 2018 an announcement of Arista products incorporating the Tomahawk-3 revealed that packet buffer is 64 MB.