As noted in the September 2014 press release, Broadcom is sampling their first switch chip that uses 25 Gb/s SERDES. The Trident chips used a 10 Gb/s SERDES and presents 10 G and 40 G ports. The Tomahawk steps up the SERDES speed by 2.5x. The SERDES is "Serializer / Deserializer." Its job is to convert parallel words in the switch data path to a bit stream for transmission. And it does the reverse for reception. Tomahawk (named after a nuclear missle) is the code name for the BCM56960. Rochan Sankar, director of product marketing at Broadcom says the packet memory pool is 16 Mbytes. Compare with Trident2 (12 Mbytes) and Trident+ (9 Mbytes).

Note that reports in the trade press of much larger buffer sizes are characterized by Broadcom as journalistic errors.

Update April 2015

Products are now being pre-announced. See Dell Z9100.

Update August 2015

Remember that there is a disclaimer about rumors at the top level and that material on switch devices should be used as a guide for questions-to-ask rather than an index into truth.

A birdie at a trade show said that Tomahawk is a four-core design. Chip manufacturers use multiple cores when they can't get the performance they want from a single lookup engine. As an example of a multi-core switch, see the description of Marvell's packet processor, at page six.

If the birdie is right, 16 MBytes of packet memory is divided into four 4-MB chuncks and that split sets the max microburst size that Tomahawk can absorb. It also means that the comparison of Tomahawk with Trident2 in the top paragraph is misleading because Trident is a single core design.

Ivan's Blog

Ivan Pepellnjak wrote a blog article in December 2015 with title Broadcom Tomahawk 101. Ivan has other material that is buried behind his webinar pay wall.