Buffer for the five ports on the Sup2T are on the port ASICs. From an architecture paper:

port ASIC

There are two port ASICs on the Supervisor used to provision the front panel 2 x 10GE and 3 x 1 GE ports. One port ASIC supports a single 10 GE port and a single GE port. The other port ASIC supports a single 10 GE port and two GE ports. The following list defines this port ASIC.s capabilities:

• Per-port VLAN translation
• VSL support (10 GE ports only)
• Cisco TrustSec support (802.1ae link layer encryption)
• Jumbo frames (up to 9216 bytes)
• Flow control
• 1P3Q4T (one strict priority queue, three normal round robin queues, and four Weighted Random Early Detection [WRED] thresholds per normal queue) queue structure for GE ports (this is the TX queue structure)
• 1P7Q4T (one strict priority queue, seven normal round robin queues, and four WRED thresholds per normal queue) queue structure for 10 GE ports (this is the TX queue structure)
• 1Q8T (one normal round robin queues and eight WRED thresholds for that queue) queue structure for 1 GE ports (this is the RX queue structure)
• 2Q4T (two normal round robin queues and four WRED thresholds per normal queue) queue structure for 10 GE ports (this is the RX queue structure)
• 256 MB total queue buffer (split among the front panel 10 G and 1 G ports)
• DWRR, WRR, and SRR scheduling schemes
• WRED and Tail Drop congestion management
• 802.1Q VLAN encapsulation
• ECC protection

Not Sure about buffer distribution

The Catalyst 6500 family is output port buffered. Compare with modern designs that are input port buffered and implement virtual output queues. In an output port buffered switch, the crossbar fabric is assumed to be capable of moving data quickly so that input buffer capacity requirements are low. The only cards that need big input buffers are those that where the port BW exceeds the internal speed of the fabric. These line cards are over subscribed. The Sup 2T ports do not over subscribe the crossbar connection.