Nexus 93180YC-EX

Introduced: March 2016

Front panel of 1 RU switch

Cisco custom ASIC code name Sugarbowl and now refered to as LSE (Leaf and spine engine). Claims to be the first 16 nM network ASIC. On-chip buffer memory is 40 MBytes. This switch is the logical successor to the Nexus 9372 that was introduced in September 2014. The same ASIC is used in linecards for the modular Nexus 9500 chassis: N9K-X9732C-EX, N9K-X97160YC-EX.

Cisco produced an architecture paper. The LSE (Leaf Spine Engine) is partitioned into two cores, each of which gets half the 40 MB of memory.

ASIC diagram shows two slices with 18.7 MB each

Buffer is composed of particles [cells] that are used in sufficient number to hold each frame. The maximum wasted packet memory per frame is thus 207 bytes when the last cell holds a single byte.