Introduced March 1, 2016

Model ASIC Throughput 1 GE 10 GE 25 GE 40 GE 100 GE Slice Buffer
92160YC-X ASE3 3.2 Tb/s 64 56 56 6 4 10 MB
9272Q ASE2 5.76 Tb/s - 140 - 72 - 5 MB
92304QC ASE2 6.08 Tb/s - 64 - 64 8 5 MB
9236C ASE2 7.2 Tb/s - 144 144 36 36 5 MB
92300YC ASE2 6.0 Tb/s - 48 48 18 18 5 MB

ASE = Application Spine Engine

Cisco did a raft of announcements that included 9200s. Previous version used a trident-2 along with Cisco custom ALE-2 ASIC that fixed warts in the trident-2. The new 92xx switches are full custom: ASE-2 and ASE-3. Since this web page is primarily about buffering:

This was copied out of architecture paper. The newer 9200 claims to have less memory than the older 9300. That is because the 9300 was a warts-on-a-pig product.

Note that the ASICs are built in slices with memory belonging to each slice. This is perhaps the first silicon designed to address Elephant versus Mice flows. The ASE claims to find the elephants on the fly and decrease their priority to keep the world safe for mice. Sadly, the architecture paper does not disclose the number of elephants and mice that can active in the ASE ASIC at one time.

This is good for the data center, and probably not good for big science in the wide area. In a world of 100 uS RTT, elephants can rapidly climb to fill all buffers. This starves the mice. But it is not clear this happens in WAN networking.