Mellanox announced their 100 Gb/s switch chip on June 18, 2015. In common with Broadcom's Tomahawk ASIC, it has 128 ser-des. Ser-des is the serializer-deserializer that converts words in the switch to and from a serial bit stream. Ser-des can be combined in groups of four to make QSFP 4-lane ports that can run at 100 Gb/s or 40 Gb/s. Or they can be used individually to create 25 Gb/s or 10 Gb/s ports. Both Tomahawk and Spectrum have 16 MBytes of packet memory.

Tomahawk has four switch cores while Spectrum has one. Each core manages its own packet buffer pool, so Broadcom can marshal at most 4 MBytes toward a big flow. Spectrum can dedicate the entire dynamic buffer pool to a single hot flow. Tomahawk presumably uses a 4-core design to improve lookups per second in quest of non-blocking performance. Mellanox claims non-blocking performance without a multi-core design. Mellanox is driving home the 4-core vs single core difference with a Tolly Report from March 2016. This was followed with a presentation at an Open Compute Project workshop in June 2016.

Mellanox held a series of road show events to introduce the Spectrum switches. Ours was Sept 28, 2015 at the Computer History Museam in San Jose. The hors d'oeuvre were excellent. It was not hard to find someone from the Sunnyvale facility that knew something about the product. So:

Q: How much control do we get over Spectrum's buffer allocation strategy?

A: Hooks are in the SDK. But if you use Mellanox software -- no access.

Spectrum is the first Mellanox hardware with an adjustable buffer strategy. And the first ship software is a direct port of code from a switch that did not have dynamic buffering. So the slightly longer answer is that buffer adjustment is on the feature roadmap.

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