Switches with Deep Buffers
These 1 RU switches use memory external to their switch chip(s) to provide deep buffers. Nothing should be read into the relative buffer depth of the Arista and Force10 switches. Once the decision is made to host packet memory off the switch chip, it is easy to provide obscene amounts of memory. To get sufficient speed, the design will probably use several interleaved banks -- and it becomes difficult to do this given chip densities without providing a lot of RAM.
For example, Arista claims 50 mS buffers are simultaneously available for each of its 48 Gig-E ports. That takes 300 Mbytes. Yet the 7048 has more than twice that. Something more than buffer requirements is acting here.
If your high performance computing environment includes serving Gb/s connected servers from your 10 Gb/s WAN feed, either the Force10 S60 or the Arista 7048 will assure that you can feed out line rate arrivals through the downward speed step without spilling packets. A less charitable perspective would be that the ship has sailed for 1 Gb/s connected devices and that HPC full players should get better computers.