Catalyst 4510R-E

chassis beauty shots

Catalyst 45xx switches do all the lifting on the supervisor card. Supervisor 7 and Supervisor 8 each have a single central packet buffer pool of 32 MBytes. It is promoted as an access layer switch and, as such, backplane bandwidth is over committed. On the 12-port 10 GE interface, there is at total of 12 Gb/s of bandwidth for each group of three ports.

table shows 32 MB packet memory

Cisco commissioned Miercom to verify the biggest surge that switch buffering can absorb. A portion of the report deals with burst capability measurement. I have taken the count of 1518 byte packets that can be absorbed and used that to calculate the effective TX queue size. Just because Meircom says so does not mean this is right. That there is not an inverse relationship between packet size and number of packets is suspect. The full report is