Catalyst 3550

Introduced December 2001

It is now hard to find documentation on switches from the turn of the century. If there were architecture deep dives for this switch, they are gone now. A discussion of switch buffer sizes makes it clear that at the time such info was considered proprietary. The answer for the Catalyst 3550 appears to be 2 MByte. What is not clear is whether the 3550 buffer was organized as packet or particle buffers. That makes a big difference in the effective buffering capability. The 3550 was a revolutionary introduction. It is a follow-on to the Catalyst 3500XL family and the first to be able to merge L2 and L3 into an edge product. At introduction, it was a 10/100 Mb/s switch with 1 Gig uplinks. That permitted switching to be done in a single port ASIC. Some details along with buffer size are in the data sheet.

A switch diagram from a 2003 Networkers slide deck shows the shared memory architecture. Packet payloads go into the shared memory while header info needed for routing is stored in SRAM. Satellite refers to the port ASIC [Satellite ASIC]. Shared memory is off chip.

Here are some paragraphs snipped from QOS Review:

    Queue Size Configuration on Gigabit Ports

    The 3550 switch uses central buffering. This means that there are no fixed buffer sizes per port. However, there is a fixed number of packets on a Gigabit port that can be queued. This fixed number is 4096. By default, each queue in a Gigabit port can have up to 1024 packets, regardless of the packet size. However, you can modify the way in which these 4096 packets are split among the four queues.

    Queue Management and Queue Size on Non-Gigabit Ports

    There is no queue management scheme available on 10/100-Mbps ports (no WRED or tail drop with two thresholds). All four queues are FIFO queues. There is also no maximum queue size that reserves 4096 packets for each Gigabit port. 10/100-Mbps ports store packets in each queue until it is full because of a lack of resources. You can reserve a minimum number of packets per queue. This minimum is set to 100 packets per queue by default. You can modify this min reserve value for each queue if you define different min reserve values and assign one of the values to each queue.

A Cat 3550 tutorial says that the answer is that total shared memory is 2 Mbytes in agreement with the datasheet. The funny thing is that 3550 lists buffer capacity in terms of packets instead of Bytes. Nowhere does Cisco claim that the 3550 has a particle memory architecture. I suspect that buffer memory is off-chip and there is a lot of it. All buffers are sized for a max length packet - 1500 bytes. Memory for the Gig-E ports may not be shared and therefore outside the 2 MB of shared memory used by the access ports.

Cisco has an entire book: Cisco Catalyst QoS: Quality of Service in Campus Networks [2003]. It contains an entire chapter on the Cat3550 and there is nothing that helps make this any clearer. Perhaps in 2017 it is not that important.