A product announcement introduced the tofino2 ASIC. A subsequent but really ugly data sheet contained the following table:

Technical Specifications Essentials Status Launched Product Collection Intel® Programmable Ethernet Switch Products Launch Date Q4'18 Lithography 7 nm Supplemental Information Description A 32x400G port P4 programmable Ethernet switch with maximum port bandwidth of 12.8 Tbps Embedded Options Available No Networking Specifications Frame Processing Rate 6 B pps Shared Packet Memory 64 MB CPU Interface PCIe Package Specifications Extended Temperature Options No Package Size 71.5X66mm

On March 5, 2020 Intel announced co-package optics with tofino2. The following section is from a blog posted on mccoy.com.sg, Dec 8, 2019.

2.2.3 Barefoot the Tofino 2 chip 7nm plus chiplet switch ASIC This is the first chiplet design in the Ethernet Switch market. Broadcom's 7nm Trident 4 is still a single chip design. Switch ASIC has been designed with analog and logic parts together for a long time. The analog part is actually different from the logic part in the evolution schedule. If it is a single-chip design, the analog part also has to advance with the process evolution of the logic part. If chiplet separation design is used, for example, the analog part of Barefoot uses an older process, Barefoot did not disclose, so everyone guessed from 28nm, 16nm, 12nm, and the logic part is the latest 7nm process. Chiplet not only brings process savings in the analog part, but also provides different SKUs through different chiplet configurations. Compared with the traditional single-chip design, simply disabling a part of the chip, this chiplet is much more economical. Figure 2.12 Barefoot's Tofino2 The following is a teaser from the Linley Newsletter. Mostly, the newsletter traffics in information about CPUs. The full article is available for $95. Linley Newsletter Barefoot Joins 400GbE-Switch Club January 8, 2019 Author: Bob Wheeler Barefoot Networks plans to bring programmability to 400G Ethernet (400GbE), and its past performance suggests it can. This month, it preannounced its Tofino 2 second-generation switch chip for 1H19 sampling. Employing 50Gbps PAM4 serdes, the new product delivers 12.8Tbps of bandwidth—double that of the first Tofino. Like its predecessor, Tofino 2 is programmable using the P4 language. It’s also the first announced 12.8Tbps switch using 7nm technology, promising lower power than 16nm designs achieve. Tofino 2 uses the same number of pipelines as the shipping Tofino. The only architectural change between generations is packet-processing extensions (dubbed PPX) to the match+action units (MAUs), but Barefoot withheld details. The company created three Tofino 2 families: the U (ultra) family provides the most MAUs and associated memory, the M (mainstream) family implements fewer MAUs, and the H (hyperscale) family omits PPX and offers the lowest latency. The 12.8Tbps versions handle 32x400GbE, 128x100GbE, and 256x50GbE ports. Barefoot will also sell 8.0Tbps and 6.4Tbps versions. Tofino 2 samples will trail those of Broadcom’s 12.8Tbps Tomahawk 3 by about 18 months. Furthermore, Broadcom and Innovium have both started production of their respective 12.8Tbps chips, enabling the first high-density 400GbE switch systems. On the plus side, Barefoot’s use of 7nm technology should deliver superior power dissipation for the new design. The startup has demonstrated that a programmable switch chip can directly compete with a fixed-function device, minimizing any programmability “tax.”