If it helps, the SerDes on the ASIC run at 50 Gb/s. The switch has 12 reverse gearbox chips which can present 96 lanes as 48 100 Gb/s QSFP28 ports. Sadly, it does not appear that there is a datasheet. There is, however, an OpenCompute design package.

While the Jericho2 ASIC does have 112 fabric ports it appears that these are not brought out as panel jacks. For access to the fabric ports, see the S9700-53DX