Internally the 600x is built with modules that can host 12-ports at 10 Gb/s or -- by running pathways in parallel -- 3-ports at 40 Gb/s. The 6004 has 48 fixed ports and 4 empty slots that can take 12 port expansion modules. The 6001 is a fixed configuration that has 48 10 Gb/s ports and 4 QSFP ports.

The relationship between the 6001 and 6004 requires some imagination and extrapolation. It is a good guess that they're using the same technology and ASICs and therefore have very similar buffer characteristics.

Each ASIC has 25 MBytes of packet buffers that is split between 16 MByte of VoQ input buffers and 9 Mbyte of output buffers. Some of the input buffers are dedicated per port, setting a max of 13.2 Mbytes in the shared pool when the ASIC is running in 10 Gb/s mode and somewhat more when in 40 Gb/s mode -- because there are fewer ports. Cisco exposes a knob that permits the size of the shared pool to be adjusted down from the maximum.

Some industry pundits believe that ASIC is a souped up version of the chip running in the 3548. They lament that Cisco won't release even the code name for the IC. It seems likely that the packet memory associated with each ASIC is integrated on the chip. But we don't know that for sure.