Introduced December 5 2016. The Cavium Xpliant switch silicon is a single core design
with 24 MB of packet memory in a single pool. Arista has put out an
architecture paper. The three variants above
represent ways that 128 SERDES can be distributed across the front panel ports that will
fit in a 1 RU form factor. At the top of the heap, the 48Y has 48 SFP28 ports and
6 QSFP28 100 Gb/s ports.
The 48T has 48 10 G-base-T ports and 6 QSFP28 100 Gb/s ports. The 32CQ has 32 QSFP28 ports.
The 7160 Series incorporates an advanced traffic manager with 24MB of packet buffer that is fully shared across all ports and is an excellent choice for scalable datacenters and modern intensive workloads. Unlike architectures where the total buffer is statically allocated to a port or group of ports or the packet memory or buffers are formed of multiple slices, the 7160 Series packet buffer is dynamically allocated across all ports with the ability to adjust in real time to the demands of bursty applications, mixed interface speeds and congestion.
To optimize the memory performance, the 24MB is divided into 96K pages of 256 byte cells, organized in 16 banks each of 1.5MB. This ensures an even distribution of page usage over the total memory. A cell can contain a single packet, or a linked list of 256 byte cells is used to buffer packets larger than a single cell. The packet buffer is carved by software into multiple shared pools to handle high priority traffic and Priority Flow Control (PFC) enabled ports separately from the other traffic. This ensures the switch packet buffer is optimally allocated for the specific use case.s unique requirements.
Extensive support for Active Queue Management mechanisms such as WRED, DCTCP and ECN ensure that both high priority flows and lossless storage traffic are handled equally well with the ability to absorb large bursts with extensive counters for visibility and accounting.
* Not currently supported in EOS