Data sheet date is 15 December 2016
The evidence so far that the Tomahawk+ exists is buried in the "X2" in the model
number. Compare with 7050X2 switches.
The most prominent distinguishing feature is that buffer memory is 22 MByte.
That is 4.5 MB per core. UCSC has one of these switches, so:
scidmz-core#sh platform trident l3 summ
Front panel chip model: bcm56965
From Q&A (November 2016)
What are the advantages of buffer allocation on the 7060X series?
The 7060X/7260X series provides a best of both worlds approach to buffering. Combining a shared/dynamic
buffer architecture with a small segment size, which together are designed to ensure maximum efficiency by
minimizing ‘unusable’ buffer space. In addition the 7060CX and 7260CX switches have 133% of total buffer
compared with the 7050X platforms. The 7060X2 series expand this resource by a further 40% to 22MB to
enhance the buffer capabilities in lossless networks, for example IP storage.
One year later, the same FAQ document added a single sentence to the
The 7260X3 series expands the
packet buffer by 2X to 42MB while maintaining the consistent buffer architecture delivering high performance,
high density and low latency switching.
Speculation: The CX2 is a Tomahawk+ while the CX3
is a Tomahawk-II. If that is true, the CX3 has a single
switch ASIC behind all the ports in the 2RU chassis.