Arista 7060CX-32 and 7260CX-64

Introduced Sept 14 2015

Arista becomes third to announce products based on Broadcom's Tomahawk switch chip. The 7060 and 7260 Tomahawk products have 25 Gb/s SERDES that can run at 25 or 10 Gb/s and therefore supporting port speeds of 10, 25, 40, 50 and 100 Gb/s. Not sure what the QX is. The 7260 appears to be made from four Tomahawks with half the ports used to support chip-to-chip interconnect. Note that 1 Gb/s is not a legal speed for the SFP+ ports. There are two SFP+ ports that can run downspeed.

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7060CX-32 7260QX-64 7260CX-64
Switch Height 1RU 2RU 2RU
Ports 32 x QSFP100
2 x SFP+		 64 x QSFP+
2 x SFP+		 64 x QSFP100
2 x SFP+
Max. 10GbE Density 130 2 258
Max. 25GbE Density 128 -- 256
Max. 40GbE Density 32 64 64
Max. 50GbE Density 64 -- 128
Max. 100GbE Density 32 -- 64
Max. I/O Rate (Tbps) 6.4Tbps 5.12Tbps 12.8Tbps
Max. Forwarding Rate 3.3Bpps 3.3Bpps 9.52Bpps
Latency 450ns 550ns 550 to 1500ns
Packet Buffer Memory 16MB 64MB
Airflow Direction Front-to-Back or Back-to-Front
As noted elsewhere, Tomahawk has four switch cores, each with a lookup engine and each with its own 4 MByte memory buffer pool. Dynamic buffering happens within the domain of a single core. Buffers cannot be loaned to other cores. So for bursty best effort traffic, the most buffer that can be claimed by a single core is 3 MByte -- depending on how much is reserved for dedicated port buffers.

Arista has published a QandA doc for the new switches. Since we are particularly interested in buffers:

What are the advantages of buffer allocation on the 7060X series?

The 7060X/7260X series provides a best of both worlds approach to buffering. Combining a shared/dynamic buffer architecture with a small segment size, which together are designed to ensure maximum efficiency by minimizing ‘unusable’ buffer space. In addition the 7060CX and 7260CX switches have 133% of total buffer compared with the 7050X platforms.

It is not clear that best of both worlds is anything new. Arista's Martin Hull described a similar system in a 2013 paper that accompanied introduction of Trident II products. What Tomahawk promises to bring is more buffer and, for highly bursty data transfers, the allocation of this memory to cores puts Arista's claims in the disingenuous category. Note that depending on the location of the input and output ports, a packet might touch a single switch core or it might touch two cores. It is possible that it might taste of two memory pools. If the internal connections between the cores are flow-controlled, perhaps the effective buffer size might be 4+4 = 8 MByte. No one has said this yet, and we'll be watching. In any case, this is still less buffer than the single core trident+ and trident2.