beauty shot shows 4 MB buffer

block diagram

Introduced in Summer of 2013. It is the successor to the 2960S that was introduced in 2010. Cisco claims that packet memory has been doubled. The block diagram shows a single buffer pool across all ports.

Information on the 2960S is somewhat harder to find. Pictures of the switch circuit board show two ASICs in the 48 port model and one ASIC in the 24 port model. It may be that the 2 MB of packet memory is actually two 1 MB pools. In any case, the new 2960-X has more. It is likely that some of the memory is dedicated to the stacking ports. Details on how much memory is in the dynamic pool available to payload packets is not known.