Daniel Sanchez

Assistant Professor, MIT EECS

Welcome to my webpage! I am an Assistant Professor at MIT's Electrical Engineering and Computer Science Department, a member of the Computer Science and Artificial Intelligence Laboratory, and hold the TIBCO Career Development Professorship. I work in computer architecture and computer systems. My current research focuses on large-scale multicores with hundreds to thousands of cores, scalable and efficient memory hierarchies, architectures with quality-of-service guarantees, and scalable runtimes and schedulers.

Before joining MIT in September 2012, I earned a Ph.D. in Electrical Engineering from Stanford University, where I worked with Professor Christos Kozyrakis. I have also received an M.S. in Electrical Engineering from Stanford (2009) and a B.S. in Telecommunications Engineering from the Technical University of Madrid, UPM (2007).

You can access my Curriculum Vitae here.

Teaching

• Spring 2014: 6.823 Computer System Architecture
  
• Fall 2013: 6.004 Computation Structures
  
• Spring 2013: 6.888 Parallel and Heterogeneous Computer Architecture
  
• Fall 2012: 6.004 Computation Structures (recitations)
  

Students

• Nathan Beckmann (Ph.D.)
  
• Harshad Kasture (Ph.D.)
  
• Mark Jeffrey (S.M./Ph.D.)
  
• Po-An Tsai (S.M./Ph.D.)
  
• Cong Yan (S.M./Ph.D.)
  
• Suvinay Subramanian (Ph.D., coadvised with Li-Shiuan Peh)
  
• Rishabh Kabra (UROP)
  

Publications

• Ubik: Efficient Cache Sharing with Strict QoS for Latency-Critical Workloads, Harshad Kasture, Daniel Sanchez, in Proceedings of the 19th international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-19), March 2014 (to appear)
  [paper] [bibtex]

• Jigsaw: Scalable Software-Defined Caches, Nathan Beckmann, Daniel Sanchez, in Proceedings of the 22nd international conference on Parallel Architectures and Compilation Techniques (PACT-22), September 2013
  [paper] [talk] [bibtex]

• Jigsaw: Scalable Software-Defined Caches (Extended Version), Nathan Beckmann, Daniel Sanchez, Technical Report MIT-CSAIL-TR-2013-017, Massachusetts Institute of Technology, July 2013
  [paper] [bibtex]

• ZSim: Fast and Accurate Microarchitectural Simulation of Thousand-Core Systems, Daniel Sanchez, Christos Kozyrakis, in Proceedings of the 40th International Symposium in Computer Architecture (ISCA-40), June 2013
  [paper] [talk] [bibtex] [source code will be available soon]

• Hardware and Software Techniques for Scalable Thousand-Core Systems, Daniel Sanchez, Ph.D. Thesis, Stanford University, August 2012
  [thesis] [defense talk] [bibtex]

• Scalable and Efficient Fine-Grain Cache Partitioning with Vantage, Daniel Sanchez, Christos Kozyrakis, in IEEE Micro's Top Picks from the Computer Architecture Conferences, May/June 2012
  [paper] [bibtex]

• SCD: A Scalable Coherence Directory with Flexible Sharer Set Encoding, Daniel Sanchez, Christos Kozyrakis, in Proceedings of the 18th international symposium on High Performance Computer Architecture (HPCA-18), February 2012
  [paper] [talk] [bibtex]

• Dynamic Fine-Grain Scheduling of Pipeline Parallelism, Daniel Sanchez, David Lo, Richard M. Yoo, Jeremy Sugerman, Christos Kozyrakis, in Proceedings of the 20th international conference on Parallel Architectures and Compilation Techniques (PACT-20), October 2011
  [paper] [talk] [bibtex]

• Vantage: Scalable and Efficient Fine-Grain Cache Partitioning, Daniel Sanchez, Christos Kozyrakis, in Proceedings of the 38th International Symposium in Computer Architecture (ISCA-38), June 2011 (selected for IEEE Micro’s Top Picks special issue of "most significant papers in computer architecture based on novelty and long-term impact" from 2011)
  [paper] [talk] [bibtex]

• The ZCache: Decoupling Ways and Associativity, Daniel Sanchez, Christos Kozyrakis, in Proceedings of the 43rd annual IEEE/ACM international symposium on Microarchitecture (MICRO-43), December 2010
  [paper] [talk] [bibtex]

• Evaluating Bufferless Flow Control for On-Chip Networks, George Michelogiannakis, Daniel Sanchez, William J. Dally, Christos Kozyrakis, in Proceedings of the 4th ACM/IEEE international symposium on Networks-on-Chip (NOCS-2010), May 2010
  [paper] [talk] [bibtex]

• An Analysis of On-Chip Interconnection Networks for Large-Scale Chip Multiprocessors, Daniel Sanchez, George Michelogiannakis, Christos Kozyrakis, in ACM Transactions on Architecture and Code Optimization (TACO), Volume 7, Issue 1, April 2010
  [paper] [bibtex]

• Flexible Architectural Support for Fine-Grain Scheduling, Daniel Sanchez, Richard M. Yoo, Christos Kozyrakis, in Proceedings of the 15th international conference on Architectural Support for Programming Languages and Operating Systems (ASPLOS-XV), March 2010
  [paper] [talk] [bibtex]

• Implementing Signatures for Transactional Memory, Daniel Sanchez, Luke Yen, Mark D. Hill, Karthikeyan Sankaralingam, in Proceedings of the 40th annual IEEE/ACM international symposium on Microarchitecture (MICRO-40), December 2007
  [paper] [talk] [bibtex]

• Design and Implementation of Signatures for Transactional Memory Systems, Daniel Sanchez, Technical Report CS-TR-2007-1611, University of Wisconsin-Madison, September 2007
  [paper] [talk] [bibtex]